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ltc3407-2 1 34072fa applicatio s u features typical applicatio u descriptio u pdas/palmtop pcs digital cameras cellular phones portable media players pc cards wireless and dsl modems high efficiency: up to 95% very low quiescent current: only 40 a 2.25mhz constant frequency operation high switch current: 1.2a on each channel no schottky diodes required low r ds(on) internal switches: 0.35 current mode operation for excellent line and load transient response short-circuit protected low dropout operation: 100% duty cycle ultralow shutdown current: i q < 1 a output voltages from 5v down to 0.6v power-on reset output externally synchronizable oscillator small thermally enhanced msop and 3mm 3mm dfn packages dual synchronous, 800ma, 2.25mhz step-down dc/dc regulator the ltc ? 3407-2 is a dual, constant frequency, synchro- nous step down dc/dc converter. intended for low power applications, it operates from 2.5v to 5.5v input voltage range and has a constant 2.25mhz switching frequency, allowing the use of tiny, low cost capacitors and inductors with a profile 1.2mm. each output voltage is adjustable from 0.6v to 5v. internal synchronous 0.35 , 1.2a power switches provide high efficiency without the need for external schottky diodes. a user selectable mode input is provided to allow the user to trade-off noise ripple for low power efficiency. burst mode ? operation provides high efficiency at light loads, while pulse skip mode provides low noise ripple at light loads. to further maximize battery life, the p-channel mosfets are turned on continuously in dropout (100% duty cycle), and both channels draw a total quiescent current of only 40 a. in shutdown, the device draws <1 a. ltc3407-2 efficiency curve figure 1. 2.5v/1.8v at 800ma step-down regulators run2 v in v in = 2.5v* to 5.5v v out2 = 2.5v at 800ma v out1 = 1.8v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407-2 c1 10 f r5 100k reset c4, 22pf c5, 22pf l1 2.2 h l2 2.2 h r4 887k r2 604k r1 301k r3 280k c3 10 f c2 10 f 3407 ta01 c1, c2, c3: taiyo yuden jmk316bj106ml l1, l2: murata lqh32cn2r2m33 *v out connected to v in for v in 2.8v load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3407 ta02 v in = 3.3v burst mode operation no load on other channel 2.5v 1.8v , lt, ltc, ltm, and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc3407-2 2 34072fa top view dd package 10-lead (3mm 3mm) plastic dfn dd pin 11, exposed pad: pgnd must be connected to gnd 10 11 9 6 7 8 4 5 3 2 1 v fb2 run2 por sw2 mode/ sync v fb1 run1 v in sw1 gnd v in voltages.................................................e 0.3v to 6v v fb1 , v fb2 , run1, run2 voltages ..................................... e 0.3v to v in + 0.3v mode/sync voltage ...................... e 0.3v to v in + 0.3v sw1, sw2 voltage ......................... e 0.3v to v in + 0.3v por voltage ................................................e 0.3v to 6v absolute axi u rati gs w ww u (note 1) ambient operating temperature range (note 2) ltc3407e-2 ........................................ e 40 c to 85 c ltc3407i-2 ...................................... e 40 c to 125 c junction temperature (note 5) ............................. 125 c storage temperature range ................. e 65 c to 150 c lead temperature (soldering, 10 sec) mse package only ........................................... 300 c reflow peak body temperature ............................ 260 c t jmax = 125 c, ja = 45 c/w, jc = 10 c/w t jmax = 125 c, ja = 45 c/w, jc = 10 c/w top view 1 2 3 4 5 v fb1 run1 v in sw1 gnd 10 9 8 7 6 v fb2 run2 por sw2 mode/ sync 11 mse package 10-lead plastic msop mse pin 11, exposed pad: pgnd must be connected to gnd pi co figuratio uuu order i for atio uu w lead free finish tape and reel part marking* package description temperature range LT3407EDD-2#pbf LT3407EDD-2#trpbf lbfb 10-lead (3mm x 3mm) plastic dfn e 40 c to 85 c lt3407idd-2#pbf lt3407idd-2#trpbf lbfb 10-lead (3mm x 3mm) plastic dfn e 40 c to 125 c lt3407emse-2#pbf lt3407emse-2#trpbf ltbdz 10-lead plastic msop e 40 c to 85 c lt3407imse-2#pbf lt3407imse-2#trpbf ltbdz 10-lead plastic msop e 40 c to 125 c lead based finish tape and reel part marking* package description temperature range LT3407EDD-2 LT3407EDD-2#tr lbfb 10-lead (3mm x 3mm) plastic dfn e 40 c to 85 c lt3407idd-2 lt3407idd-2#tr lbfb 10-lead (3mm x 3mm) plastic dfn e 40 c to 125 c lt3407emse-2 lt3407emse-2#tr ltbdz 10-lead plastic msop e 40 c to 85 c lt3407imse-2 lt3407imse-2#tr ltbdz 10-lead plastic msop e 40 c to 125 c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is indicated by a label on the shipping container for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc3407-2 3 34072fa typical perfor a ce characteristics uw load step burst mode operation pulse skipping mode note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the 5ltc3407e-2 is guaranteed to meet specified performance from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3407i-2 is guaranteed over the full C 40 c to 125 c operating temperature range. note 3: the ltc3407-2 is tested in a proprietary test mode that connects v fb to the output of the error amplifier. note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja ). note 6: the dfn switch on-resistance is guaranteed by correlation to wafer level measurements. electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 3.6v, unless otherwise specified. (note 2) t a = 25 c unless other wise specified. 3407 g01 3407 g02 3407 g03 v in = 3.6v v out = 1.8v i load = 100ma circuit of figure 1 v in = 3.6v v out = 1.8v i load = 20ma circuit of figure 1 v in = 3.6v v out = 1.8v i load = 80ma to 800ma circuit of figure 1 sw 5v/div v out 100mv/div i l 200ma/div sw 5v/div v out 10mv/div i l 200ma/div v out 200mv/div i l 500ma/div i load 500ma/div 2 s/div 1 s/div 20 s/div symbol parameter conditions min typ max units v in operating voltage range 2.5 5.5 v i fb feedback pin input current 30 na v fb feedback voltage (note 3) 0 c t a 85 c 0.588 0.6 0.612 v C40 c t a 85 c 0.585 0.6 0.612 v C40 c t a 125 c (note 2) 0.585 0.6 0.612 v v line reg reference voltage line regulation v in = 2.5v to 5.5v (note 3) 0.3 0.5 %/v v load reg output voltage load regulation (note 3) 0.5 % i s input dc supply current active mode v fb1 = v fb2 = 0.5v 700 950 a sleep mode v fb1 = v fb2 = 0.63v, mode/sync = 3.6v 40 60 a shutdown run = 0v, v in = 5.5v, mode/sync = 0v 0.1 1 a f osc oscillator frequency v fbx = 0.6v 1.8 2.25 2.7 mhz f sync synchronization frequency 2.25 mhz i lim peak switch current limit v in = 3v, v fbx = 0.5v, duty cycle <35% 0.95 1.2 1.6 a r ds(on) top switch on-resistance (note 6) 0.35 0.45 bottom switch on-resistance (note 6) 0.30 0.45 i sw(lkg) switch leakage current v in = 5v, v run = 0v, v fbx = 0v 0.01 1 a por power-on reset threshold v fbx ramping up, mode/sync = 0v 8.5 % v fbx ramping down, mode/sync = 0v C8.5 % power-on reset on-resistance 100 200 power-on reset delay 262,144 cycles v run run threshold 0.3 1 1.5 v i run run leakage current 0.01 1 a
ltc3407-2 4 34072fa efficiency vs load current efficiency vs load current load regulation typical perfor a ce characteristics uw reference voltage vs temperature r ds(on) vs input voltage r ds(on) vs temperature v in (v) 1 500 450 400 350 300 250 200 46 3407 g08 2 3 57 r ds(on) (m ) main switch synchronous switch 0.615 0.610 0.605 0.600 0.595 0.590 0.585 reference voltage (v) temperature ( c) C50 550 500 450 400 350 300 250 200 150 100 25 75 3407 g09 C25 0 50 100 150 125 temperature ( c) C50 25 75 3407 g07 C25 0 50 100 125 r ds(on) (m ) main switch synchronous switch v in = 3.6v v in = 3.6v v in = 4.2v v in = 2.7v t a = 25 c load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3407 g10 3.6v 2.7v 4.2v v out = 2.5v burst mode operation no load on other channel circuit of figure 1 load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3407 g11 v in = 3.6v, v out = 1.8v no load on other channel load current (ma) 1 v out error (%) 4 3 2 1 0 C1 C2 C3 C4 10 100 1000 3407 g12 v in = 3.6v, v out = 1.8v no load on other channel burst mode operation burst mode operation pulse skip mode pulse skip mode 2.5 2.4 2.3 2.2 2.1 2.0 frequency (mhz) 10 8 6 4 2 0 C2 C4 C6 C8 C10 frequency deviation (%) supply voltage (v) 2 3407 g06 3 456 input voltage (v) 2 3407 g04 3 456 temperature ( c) C50 25 75 3407 g05 C25 0 50 100 125 100 95 90 85 80 75 70 65 60 efficiency (%) v out = 1.8v burst mode operation circuit of figure 1 800ma 10ma 100ma 1ma v in = 3.6v efficiency vs input voltage oscillator frequency vs supply voltage oscillator frequency vs temperature t a = 25 c unless other wise specified.
ltc3407-2 5 34072fa v fb1 (pin 1): output feedback. receives the feedback voltage from the external resistive divider across the output. nominal voltage for this pin is 0.6v. run1 (pin 2): regulator 1 enable. forcing this pin to v in enables regulator 1, while forcing it to gnd causes regu- lator 1 to shut down. v in (pin 3): main power supply. must be closely decoupled to gnd. sw1 (pin 4): regulator 1 switch node connection to the inductor. this pin swings from v in to gnd. gnd (pin 5): main ground. connect to the (C) terminal of c out , and (C) terminal of c in . mode/sync (pin 6): combination mode selection and oscillator synchronization. this pin controls the operation of the device. when tied to v in or gnd, burst mode operation or pulse skipping mode is selected, respec- tively. do not float this pin. the oscillation frequency can uu u pi fu ctio s be syncronized to an external oscillator applied to this pin and pulse skipping mode is automatically selected. sw2 (pin 7): regulator 2 switch node connection to the inductor. this pin swings from v in to gnd. por (pin 8): power-on reset . this common-drain logic output is pulled to gnd when the output voltage is not within 8.5% of regulation and goes high after 117ms when both channels are within regulation. run2 (pin 9): output feedback. forcing this pin to v in enables regulator 2, while forcing it to gnd causes regu- lator 2 to shut down. v fb2 (pin 10): output feedback. receives the feedback voltage from the external resistive divider across the output. nominal voltage for this pin is 0.6v. exposed pad (gnd) (pin 11): power ground. connect to the (C) terminal of c out , and (C) terminal of c in . must be connected to electrical ground on pcb. typical perfor a ce characteristics uw v in (v) 2 v out error (%) 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 4 6 3407 g15 35 v out = 1.8v i out = 200ma t a = 25 c load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3407 g13 2.7v 4.2v v out = 1.2v burst mode operation no load on other channel circuit of figure 1 load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3407 g14 2.7v 4.2v v out = 1.5v burst mode operation no load on other channel circuit of figure 1 3.6v 3.6v efficiency vs load current efficiency vs load current line regulation t a = 25 c unless other wise specified.
ltc3407-2 6 34072fa the ltc3407-2 uses a constant frequency, current mode architecture. the operating frequency is set at 2.25mhz and can be synchronized to an external oscillator. both channels share the same clock and run in-phase. to suit a variety of applications, the selectable mode pin allows the user to choose between low noise and high efficiency. the output voltage is set by an external divider returned to the v fb pins. an error amplfier compares the divided output voltage with a reference voltage of 0.6v and adjusts the peak inductor current accordingly. overvoltage and undervoltage comparators will pull the por output low if the output voltage is not within 8.5%. the por output will go high after 262,144 clock cycles (about 117ms) of achieving regulation. operatio u block diagra w 1 2 9 10 8 3 4 11 5 C + C + C + C + ea uvdet ovdet 0.6v 7 0.65v 0.55v C + 0.35v uv ov i th switching logic and blanking circuit s r q q rs latch burst C + i comp i rcmp anti shoot- thru burst clamp slope comp en sleep por counter 0.6v ref osc osc regulator 2 (identical to regulator 1) pgood1 pgood2 shutdown v in v in v in 6 regulator 1 sw1 gnd por gnd sw2 5 mode/sync v fb1 run1 run2 v fb2 main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle when the v fb voltage is below the the reference voltage. the current into the inductor and the load increases until the current limit is reached. the switch turns off and energy stored in the inductor flows through the bottom switch (n-channel mosfet) into the load until the next clock cycle. the peak inductor current is controlled by the internally compensated i th voltage, which is the output of the error amplifier.this amplifier compares the v fb pin to the 0.6v reference. when the load current increases, the v fb volt- age decreases slightly below the reference. this
ltc3407-2 7 34072fa decrease causes the error amplifier to increase the i th voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the run pin to ground. low current operation two modes are available to control the operation of the ltc3407-2 at low currents. both modes automatically switch from continuous operation to the selected mode when the load current is low. to optimize efficiency, the burst mode operation can be selected. when the load is relatively light, the ltc3407-2 automatically switches into burst mode operation, in which the pmos switch operates intermittently based on load demand with a fixed peak inductor current. by run- ning cycles periodically, the switching losses which are dominated by the gate charge losses of the power mosfets are minimized. the main control loop is interrupted when the output voltage reaches the desired regulated value. a hysteretic voltage comparator trips when i th is below 0.35v, shutting off the switch and reducing the power. the output capacitor and the inductor supply the power to the load until i th exceeds 0.65v, turning on the switch and the main control loop which starts another cycle. for lower ripple noise at low currents, the pulse skipping mode can be used. in this mode, the ltc3407-2 continues to switch at a constant frequency down to very low currents, where it will begin skipping pulses. the effi- ciency in pulse skip mode can be improved slightly by connecting the sw node to the mode/sync input which reduces the clock frequency by approximately 30%. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. an important design consideration is that the r ds(on) of the p-channel switch increases with decreasing input supply voltage (see typical performance characteristics). therefore, the user should calculate the power dissipation when the ltc3407-2 is used at 100% duty cycle with low input voltage (see thermal considerations in the applica- tions information section). low supply operation to prevent unstable operation, the ltc3407-2 incorpo- rates an under-voltage lockout circuit which shuts down the part when the input voltage drops below about 1.65v. operatio u applicatio s i for atio wu uu a general ltc3407-2 application circuit is shown in figure 2. external component selection is driven by the load requirement, and begins with the selection of the inductor l. once the inductor is chosen, c in and c out can be selected. inductor selection although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance and increases with higher v in or v out : = ? ? ? ? ? ? i v fl v v l out o out in ? ?C 1 accepting larger values of i l allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. a reasonable starting point for setting ripple current is i l = 0.3 ? i lim , where i lim is the peak switch current limit. the largest ripple current i l occurs at the maximum input voltage. to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l v fi v v out ol out in max = ? ? ? ? ? ? ? ?C () 1 the inductor value will also have an effect on burst mode operation. the transition from low current operation
ltc3407-2 8 34072fa table 1. representative surface mount inductors part value dcr max dc size number ( h) ( max) current (a) w l h (mm 3 ) sumida 2.2 0.075 1.20 3.8 3.8 1.8 cdrh3d16 3.3 0.110 1.10 4.7 0.162 0.90 sumida 1.5 0.068 0.900 3.2 3.2 1.2 cdrh2d11 2.2 0.170 0.780 sumida 2.2 0.116 0.950 4.4 5.8 1.2 cmd4d11 3.3 0.174 0.770 murata 1.0 0.060 1.00 2.5 3.2 2.0 lqh32cn 2.2 0.097 0.79 toko 2.2 0.060 1.08 2.5 3.2 2.0 d312f 3.3 0.260 0.92 panasonic 3.3 0.17 1.00 4.5 5.4 1.2 elt5kt 4.7 0.20 0.95 output capacitor (c out ) selection the selection of c out is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( v out ) is deter- mined by: ?? + ? ? ? ? ? ? v i esr fc out l o out 1 8 where f = operating frequency, c out = output capacitance and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. with i l = 0.3 ? i lim the output ripple will be less than 100mv at maximum v in and f o = 2.25mhz with: esr cout < 150m once the esr requirements for c out have been met, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. alumi- num electrolytic, special polymer, ceramic and dry tantulum capacitors are all available in surface mount packages. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr(size) product of any aluminum electrolytic at a somewhat higher price. special polymer begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy mate- rials are small and dont radiate much energy, but gener- ally cost more than powdered iron core inductors with similar electrical characterisitics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/emi require- ments than on what the ltc3407-2 requires to operate. table 1 shows some typical surface mount inductors that work well in ltc3407-2 applications. input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out / v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maxi- mum rms current must be used. the maximum rms capacitor current is given by: ii vvv v rms max out in out in (C ) where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max = i lim C i l /2. this formula has a maximum at v in = 2v out , where i rms = i out/2 . this simple worst-case is commonly used to design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours life- time. this makes it advisable to further derate the capaci- tor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1 f to 1 f ceramic capacitor is also recom- mended on v in for high frequency decoupling, when not using an all ceramic capacitor solution. applicatio s i for atio wu u u
ltc3407-2 9 34072fa capacitors, such as sanyo poscap, panasonic special polymer (sp), and kemet a700, offer very low esr, but have a lower capacitance density than other types. tanta- lum capacitors have the highest capacitance density, but they have a larger esr and it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors have a signifi- cantly larger esr, and are often used in extremely cost- sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have the lowest esr and cost, but also have the lowest capacitance density, a high voltage and tempera- ture coefficient, and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with trace inductance can lead to significant ringing. in most cases, 0.1 f to 1 f of ceramic capacitors should also be placed close to the ltc3407-2 in parallel with the main capacitors for high frequency decoupling. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. these are tempt- ing for switching regulator use because of their very low esr. unfortunately, the esr is so low that it can cause loop stability problems. solid tantalum capacitor esr generates a loop zero at 5khz to 50khz that is instrumen- tal in giving acceptable loop phase margin. ceramic ca- pacitors remain capacitive to beyond 300khz and usually resonate with their esl before esr becomes effective. also, ceramic caps are prone to temperature effects which applicatio s i for atio wu u u figure 2. ltc3407-2 general schematic run2 v in v in = 2.5v to 5.5v v out2 v out1 run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407-2 c in r5 power-on reset c4 c5 l1 l2 r4 r2 r1 r3 c out2 c out1 3407 f02 ps* bm* *mode/sync = 0v: pulse skip mode/sync = v in : burst mode requires the designer to check loop stability over the operating temperature range. to minimize their large temperature and voltage coefficients, only x5r or x7r ceramic capacitors should be used. a good selection of ceramic capacitors is available from taiyo yuden, avx, kemet, tdk, and murata. great care must be taken when using only ceramic input and output capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically, 3-4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about 2-3 times the linear drop of the first cycle. thus, a good place to start is with the output capacitor size of approximately: c i fv out out o droop 25 . ? more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely re- quired to supply high frequency bypassing, since the impedance to the supply is very low. a 10 f ceramic capacitor is usually enough for these conditions. setting the output voltage the ltc3407-2 develops a 0.6v reference voltage be- tween the feedback pin, v fb , and the ground as shown in figure 2. the output voltage is set by a resistive divider according to the following formula:
ltc3407-2 10 34072fa hot swap is registered trademark of linear technology corporation. vv r r out =+ ? ? ? ? ? ? 06 1 2 1 . keeping the current small (<5 a) in these resistors maxi- mizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. to improve the frequency response, a feed-forward ca- pacitor c f may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. power-on reset the por pin is an open-drain output which pulls low when either regulator is out of regulation. when both output voltages are within 8.5% of regulation, a timer is started which releases por after 2 18 clock cycles (about 117ms). this delay can be significantly longer in burst mode operation with low load currents, since the clock cycles only occur during a burst and there could be milliseconds of time between bursts. this can be bypassed by tying the por output to the mode/sync input, to force pulse skipping mode during a reset. in addition, if the output voltage faults during burst mode sleep, por could have a slight delay for an undervoltage output condition and may not respond to an overvoltage output. this can be avoided by using pulse skipping mode instead. when either chan- nel is shut down, the por output is pulled low, since one or both of the channels are not in regulation. mode selection & frequency synchronization the mode/sync pin is a multipurpose pin which provides mode selection and frequency synchronization. connect- ing this pin to v in enables burst mode operation, which provides the best low current efficiency at the cost of a higher output voltage ripple. connecting this pin to ground selects pulse skipping mode, which provides the lowest output ripple, at the cost of low current efficiency. the ltc3407-2 can also be synchronized to an external 2.25mhz clock signal by the mode/sync pin. during synchronization, the mode is set to pulse skipping and the top switch turn-on is synchronized to the rising edge of the external clock. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second- order overshoot/dc ratio cannot be used to determine phase margin. in addition, a feed-forward capacitor, c f , can be added to improve the high frequency response, as shown in figure 2. capacitor c f provides phase lead by creating a high frequency zero with r2, which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to applica- tion note 76. in some applications, a more severe transient can be caused by switching in loads with large (>1 f) input capacitors. the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this prob- lem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap tm controller is designed specifically for this purpose and usually incorpo- rates current limiting, short-circuit protection, and soft- starting. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would applicatio s i for atio wu u u
ltc3407-2 11 34072fa produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% - (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, 4 main sources usually account for most of the losses in ltc3407-2 circuits: 1)v in quiescent current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1) the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. 2) the switching current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continu- ous mode, i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l, but is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out2 (r sw + r l ) 4) other hidden losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching fre- quency. other losses including diode conduction losses during dead-time and inductor core losses generally ac- count for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3407-2 does not dissipate much heat due to its high efficiency. however, in applications where the ltc3407-2 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150 c, both power switches will turn off and the sw node will become high impedance. to prevent the ltc3407-2 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera- ture rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as an example, consider the case when the ltc3407-2 is in dropout on both channels at an input voltage of 2.7v with a load current of 800ma and an ambient temperature of 70 c. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the main switch is 0.425 . therefore, power dissipated by each channel is: p d = i 2 ? r ds(on) = 272mw the ms package junction-to-ambient thermal resistance, ja , is 45 c/w. therefore, the junction temperature of the applicatio s i for atio wu u u
ltc3407-2 12 34072fa figure 3. ltc3407-2 layout diagram (see board layout checklist) run2 v in v in v out2 v out1 run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407-2 c in c4 c5 l1 l2 r4 r2 r1 r3 c out2 c out1 3407 f03 bold lines indicate high current paths regulator operating in a 70 c ambient temperature is approximately: t j = 2 ? 0.272 ? 45 + 70 = 94.5 c which is below the absolute maximum junction tempera- ture of 125 c. design example as a design example, consider using the ltc3407-2 in an portable application with a li-ion battery. the battery provides a v in = 2.8v to 4.2v. the load requires a maxi- mum of 800ma in active mode and 2ma in standby mode. the output voltage is v out = 2.5v. since the load still needs power in standby, burst mode operation is selected for good low load efficiency. first, calculate the inductor value for about 30% ripple current at maximum v in : l v mhz ma v v h = ? ? ? ? ? ? = 25 2 25 300 1 25 42 15 . .? ?C . . . choosing a vendors closest inductor value of 2.2 h, results in a maximum ripple current of: = ? ? ? ? ? ? ? = i v mhz v v ma l 25 225 22 1 25 42 204 . .?. ? . . for cost reasons, a ceramic capacitor will be used. c out selection is then based on load step droop instead of esr requirements. for a 5% output droop: c ma mhz v f out = 25 800 225 5 25 71 . .?(%?.) . a good standard value is 10 f. since the output imped- ance of a li-ion battery is very low, c in is typically 10 f. the output voltage can now be programmed by choosing the values of r1 and r2. to maintain high efficiency, the current in these resistors should be kept small. choosing 2 a with the 0.6v feedback voltage makes r1~300k. a close standard 1% resistor is 280k, and r2 is then 887k. the pgood pin is a common drain output and requires a pull-up resistor. a 100k resistor is used for adequate speed. figure 1 shows the complete schematic for this design example. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3407-2. these items are also illustrated graphically in the layout diagram of figure 3. check the following in your layout: 1. does the capacitor c in connect to the power v in (pin 3) and gnd (exposed pad) as close as possible? this capaci- tor provides the ac current to the internal power mosfets and their drivers. 2. are the c out and l1 closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 3. the resistor divider, r1 and r2, must be connected between the (+) plate of c out and a ground sense line terminated near gnd (exposed pad). the feedback signals v fb should be routed away from noisy components and traces, such as the sw line (pins 4 and 7), and its trace should be minimized. 4. keep sensitive components away from the sw pins. the input capacitor c in and the resistors r1 to r4 should be routed away from the sw traces and the inductors. 5. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the gnd pin at one point and should not share the high current path of c in or c out . 6. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. these copper areas should be con- nected to v in or gnd. applicatio s i for atio wu u u
ltc3407-2 13 34072fa low ripple buck regulators using ceramic capacitors run2 v in v in = 2.5v to 5.5v v out2 = 1.8v at 800ma v out1 = 1.2v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407-2 c1 10 f r5 100k power-on reset c4, 22pf c5, 22pf l1 4.7 h l2 4.7 h r4 887k r2 604k r1 604k r3 442k c3 10 f c2 10 f 3407 ta03 c1, c2, c3: taiyo yuden jmk316bj106ml l1, l2: sumida cdrh2d18/hp-4r7nc load current (ma) efficiency (%) 10 100 1000 3407 ta03b 100 95 90 85 80 75 70 65 60 55 50 1.8v 1.2v v in = 3.3v pulse skip mode no load on other channel efficiency vs load current typical applicatio s u
ltc3407-2 14 34072fa typical applicatio s u run2 v in v in = 3.6v to 5.5v v out2 = 3.3v at 800ma v out1 = 1.8v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407-2 c1* 4.7 f r5 100k power-on reset c4, 22pf c5, 22pf l1 2.2 h l2 2.2 h r4 887k r2 604k r1 301k r3 196k c3 4.7 f 2 c2 4.7 f 2 3407 ta07 c1, c2, c3: tdk c1608x5roj475m l1, l2: cmd4d11-2r2 *if c1 is greater than 3" from power source, additional capacitance may be required. 2mm height core supply efficiency vs load current load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3407 ta08 3.3v 1.8v v in = 5v burst mode operation no load on other channel
ltc3407-2 15 34072fa package descriptio u mse package 10-lead plastic msop (reference ltc dwg # 05-08-1664) msop (mse) 0307 rev b 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) 0.1016 0.0508 (.004 .002) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc3407-2 16 34072fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 related parts part number description comments ltc1878 600ma (i out ), 550khz, 95% efficiency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 10 a, synchronous step-down dc/dc converter i sd <1 a, msop-8, package lt1940 dual output 1.4a(i out) , constant 1.1mhz, v in : 3v to 25v, v out(min) = 1.2v, i q = 2.5ma, i sd = <1 a, high efficiency step-down dc/dc converter tssop-16e package ltc3252 dual 250ma (i out ), 1mhz, spread spectrum 88% efficiency, v in : 2.7v to 5.5v, v out(min) = 0.9v to 1.6v, inductorless step-down dc/dc converter i q = 60 a, i sd < 1 a, dfn-12 package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20 a, synchronous step-down dc/dc converters i sd <1 a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20 a, synchronous step-down dc/dc converters i sd <1 a, thinsot package lt3407 600ma, 1.5mhz 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40 a, dual synchronous step-down dc/dc converter i sd <1 a, mse, dfn package ltc3411 1.25a (i out ), 4mhz, 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60 a, synchronous step down dc/dc converter i sd <1 a, msop-10 package ltc3412 2.5a (i out ), 4mhz, 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60 a, synchronous step down dc/dc converter i sd <1 a, tssop-16e package ltc3414 4a (i out ), 4mhz, 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64 a, synchronous step down dc/dc converter i sd <1 a, tssop-28e package ltc3440 600ma (i out ), 2mhz, 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 2.5v, i q = 25 a, synchronous buck-boost dc/dc converter i sd <1 a, msop-10 package lt 0707 rev a ?printed in usa load current (ma) 1 efficiency (%) 90 80 70 60 50 40 30 10 100 1000 3407 ta05 v out = 3.3v burst mode operation no lod on other channel 4.2v 2.8v 3.6v load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 3407 ta06 v out = 1.8v burst mode operation no load on other channel 4.2v 2.8v 3.6v efficiency vs load current efficiency vs load current run2 v in v in = 2.8v to 4.2v v out2 = 3.3v at 200ma v out1 = 1.8v at 800ma run1 por sw1 v fb1 gnd v fb2 sw2 mode/sync ltc3407-2 c1 10 f r5 100k power-on reset c4, 22pf c5, 22pf l1 2.2 h l2 10 h r4 887k r2 604k r1 301k r3 196k c3 10 f c6 47 f c2 10 f 3407 ta04 + m1 d1 c1, c2, c3: taiyo yuden jmk316bj106ml c6: sanyo 6tpb47m d1: philips pmeg2010 l1: murata lqh32cn2r2m33 l2: toko a914byw-100m (d52lc series) m1: siliconix si2302 2mm height lithium-ion single inductor buck-boost regulator and a buck regulator u typical applicatio

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